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general description the max1937/max1938/max1939 comprise a family of synchronous, two-phase, step-down controllers capable of delivering load currents up to 60a. the controllers uti- lize quick-pwm control architecture in conjunction with active load-current voltage positioning. quick-pwm con- trol provides instantaneous load-step response, while programmable voltage positioning allows the converter to utilize full transient regulation limits, reducing the out- put capacitance requirement. the two phases operate 180 out-of-phase with an effective 500khz switching fre- quency, thus reducing input and output current ripple, as well as reducing input filter capacitor requirements. the max1937/max1938/max1939 are compliant with amd hammer, intel ? voltage-regulator module (vrm) 9.0/9.1, and amd athlon mobile vid code specifica- tions (see table 1 for vid codes). the internal dac pro- vides ultra-high accuracy of ?.75%. a controlled vid voltage transition is implemented to minimize both undervoltage and overvoltage overshoot during vid input change. remote sensing is available for high output-voltage accuracy. the mosfet switches are driven by a 6v gate-drive circuit to minimize switching and crossover conduction losses to achieve efficiency as high as 90%. the max1937/max1938/max1939 feature cycle- by-cycle current limit to ensure that the current limit is not exceeded. crowbar protection is available to pro- tect against output overvoltage. applications notebook and desktop computers servers and workstations blade servers high-end switches high-end routers macro base stations features ? ?.75% output voltage accuracy ? instant load-transient response ? up to 90% efficiency eliminates heatsinks ? up to 60a output current ? 8v to 24v input range ? user-programmable voltage positioning ? controlled vid voltage transition ? 500khz effective switching frequency ? max1937: amd hammer compatible ? max1938: intel vrm 9.0/9.1 compatible ? max1939: amd athlon mobile compatible ? soft-start ? power-good (pwrgd) output ? cycle-by-cycle current limit ? output overvoltage protection (ovp) ? r ds(on) or r sense current sensing ? remote voltage sensing ? 28-pin qsop package max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v cc bst1 dh1 lx1 cs1 dl1 pwrgd vlg pgnd dl2 cs2 lx2 dh2 bst2 fb en ref gnds gnd ilim v dd vpos vid4 vid3 vid2 time vid1 vid0 qsop top view max1937 max1938 max1939 pin configuration ordering information 19-2498; rev 1; 10/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max1937 eei -40 c to +85 c 28 qsop max1938 eei -40 c to +85 c 28 qsop max1939 eei -40 c to +85 c 28 qsop quick-pwm is a trademark of maxim integrated products, inc. athlon is a trademark of advanced micro devices, inc. intel is a registered trademark of intel corp. typical application circuits and functional diagram appear at end of data sheet.
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ............................................................-0.3v to +28v v dd , pwrgd, ilim, fb to gnd ...............................-0.3v to +6v en, gnds, vpos, ref, vid_, time to gnd ............................................0.3v to v vdd + 0.3v pgnd to gnd .......................................................-0.3v to +0.3v cs1, cs2 to gnd ......................................................-2v to +28v vlg to gnd..............................................................-0.3v to +7v bst1, bst2 to gnd ...............................................-0.3v to +35v lx1 to bst1..............................................................-7v to +0.3v lx2 to bst2..............................................................-7v to +0.3v dh1 to lx1.................................................-0.3v to v bst1 + 0.3v dh2 to lx2.................................................-0.3v to v bst2 + 0.3v dl1, dl2 to pgnd ......................................-0.3v to v vlg + 0.3v continuous power dissipation (t a = +70?) 28-pin qsop (derate 20.8mw/? above +70?)......860.2mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v cc = 12v, v en = v vdd = 5v, pgnd = gnds = gnd = 0, vid_ = gnd, c vpos = 47pf, c ref = 0.1?, v ilim = 1v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units general max1937 6 24 v cc operating range max1938/max1939 8 24 v v dd operating range 4.5 5 5.5 v vlg operating range v vlg > v vdd 4.5 6.5 v v cc operating supply current fb above threshold (no switching) 20 40 ? v dd operating supply current fb above threshold (no switching) 1.4 2.5 ma vlg operating supply current fb above threshold (no switching) 20 60 ? v cc shutdown current en = gnd <1 5 ? v dd shutdown current en = gnd, vid_ not connected 50 100 ? vlg shutdown current en = gnd <1 5 ? time output voltage 1.96 2.00 2.04 v ilim input bias v ilim = 1.5v -250 +250 na vpos output voltage cs_= gnd, vpos connected to ref through a 75k resistor 1.96 2.0 2.04 v reference reference voltage -50? i ref 50? 1.987 2.000 2.013 v soft-start max1937 1.1 5.5 max1938 1.5 6.2 ramp period max1939 1.3 6.5 ms soft-start voltage step 25 mv error amplifier fb input resistance resistance from fb to gnd 180 k gnds input bias current -5 +5 ? output regulation voltage accuracy -0.75 +0.75 %
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = 12v, v en = v vdd = 5v, pgnd = gnds = gnd = 0, vid_ = gnd, c vpos = 47pf, c ref = 0.1?, v ilim = 1v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units fault protection v dd undervoltage lockout (uvlo) threshold rising or falling v dd 4.00 4.25 4.45 v v dd uvlo hysteresis 80 mv vlg uvlo threshold rising or falling vlg 4.00 4.25 4.45 v vlg uvlo hysteresis 40 mv thermal shutdown rising temperature, typical hysteresis = 15? 160 ? rising edge 1.600 reference uvlo threshold falling edge 1.584 v max1937/max1938 1.97 2.00 2.03 output overvoltage fault threshold rising and falling max1939 2.215 2.250 2.285 v output uvlo threshold rising and falling percentage of the nominal regulation voltage 65 70 75 % current limit pgnd to cs_, v ilim = 1.5v 135 150 165 pgnd to cs_, v ilim = 1v 90 100 110 current-limit threshold pgnd to cs_, v ilim = 0.5v 45 50 55 mv cs input offset voltage cs_ = gnd -3 +3 mv cs_ input bias current cs_ = gnd -5 +5 ? voltage positioning vpos input offset voltage -3 +3 mv vpos gain from cs_ to fb; v cs1 , v cs2 = 0, -100mv; r vpos = 75k 72.5 75.0 77.5 %/v vpos gain from cs1, cs2 to fb; v cs1 , v cs2 = +13mv, -113mv; r vpos = 75k 68 75 82 %/v timer and drivers on-time lx1 = lx2 = cs1 = cs2 = gnd, v fb = 1.5v 420 525 630 ns minimum off-time dh1 low to dh2 high, and dh2 low to dh1 high 260 325 390 ns max1937/max1938 60 dh_ low to dl_ high max1939 60 max1937/max1938 85 break-before-make time dl_ low to dh_ high max1939 70 ns
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = 12v, v en = v vdd = 5v, pgnd = gnds = gnd = 0, vid_ = gnd, c vpos = 47pf, c ref = 0.1?, v ilim = 1v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) parameter conditions min typ max units dh_ on-resistance in low state v bst1 = v bst2 = 6v, lx1 = lx2 = gnd 1.5 3.0 dh_ on-resistance in high state v bst_ = 6v, lx_ = gnd 1.5 3.0 dl_ on-resistance in low state 0.5 1.7 dl_ on-resistance in high state 1.5 3.0 bst_ leakage current v bst_ = 30v, v lx_ = 24v 50 ? lx_ leakage current v bst_ = 30v, v lx_ = 24v 50 ? en and vid low level threshold 0.8 v high level threshold 1.6 v pullup resistance internally pulled up to v dd 50 100 200 k pwrgd pwrgd upper trip level 10.0 12.5 15.0 % pwrgd lower trip level -15 -12.5 -10 % output low level 0.4 v output high leakage 1 ? controlled vid change r time = 120k 6.17 6.67 7.25 r time = 47k 2.35 2.63 2.99 on-the-fly vid change slew rate 25mv per step r time = 470k 23.5 26.3 29.9 ? vid_ change frequency range 38 380 khz pwrgd blanking time v vdd = 4.5v to 5.5v 125 200 350 ?
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change _______________________________________________________________________________________ 5 electrical characteristics (v vcc = 12v, v en = v vdd = 5v, pgnd = gnds = gnd, vid_= gnd, c vpos = 47pf, c ref = 0.1?, v ilim = 1v, t a = -40? to +85? , unless otherwise noted.) (note 1) parameter conditions min typ max units general max1937 6 24 v cc operating range max1938/max1939 8 24 v v dd operating range 4.5 5.5 v vlg operating range v vlg v vdd 4.5 6.5 v v cc operating supply current fb above threshold (no switching) 40 ? v dd operating supply current fb above threshold (no switching) 2.5 ma vlg operating supply current fb above threshold (no switching) 20 60 ? v cc shutdown current en = gnd 5 ? v dd shutdown current en = gnd, vid_ not connected 100 ? vlg shutdown current en = gnd 5 ? time output voltage 1.96 2.04 v ilim input bias v ilim = 1v -250 +250 na vpos output voltage cs_ = gnd, vpos connected to ref through a 75k resistor 1.96 2.04 v reference reference voltage -50? i ref 50? 1.98 2.02 v soft-start max1937 1.1 5.5 max1938 1.5 6.6 ramp period max1939 1.3 7.0 ms error amplifier gnds input bias current -5 +5 ? output regulation voltage accuracy -1 +1 % fault protection v dd uvlo threshold rising or falling v dd 4.00 4.45 v vlg uvlo threshold rising or falling vlg 4.00 4.45 v max1937/max1938 1.97 2.03 output overvoltage fault threshold rising and falling max1939 2.215 2.285 v output uvlo threshold rising and falling percentage of the nominal regulation voltage 65 75 % current limit pgnd to cs_, v ilim = 1.5v 135 165 pgnd to cs_, v ilim = 1v 90 110 current-limit threshold pgnd to cs_, v ilim = 0.5v 45 55 mv
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 6 _______________________________________________________________________________________ electrical characteristics (continued) (v vcc = 12v, v en = v vdd = 5v, pgnd = gnds = gnd, vid_= gnd, c vpos = 47pf, c ref = 0.1?, v ilim = 1v, t a = -40? to +85? , unless otherwise noted.) (note 1) parameter conditions min typ max units cs input offset voltage cs_ = gnd -5 +5 mv cs_ input bias current cs_ = gnd -5 +5 ? voltage positioning vpos input offset voltage -5 +5 mv vpos gain from cs_ to fb; v cs1 , v cs2 = 0, -100mv; r vpos = 75k 72.5 77.5 %/v vpos gain from cs1, cs2 to fb; v cs1 , v cs2 = +13mv, -113mv; r vpos = 75k 68 82 %/v timer and drivers on-time lx1 = lx2 = cs1 = cs2 = gnd, v fb = 1.5v 420 630 ns minimum off-time dh1 low to dh2 high, and dh2 low to dh1 high 260 390 ns dh_ on-resistance in low state v bst1 = v bst2 = 6v, lx1 = lx2 = gnd 3 dh_ on-resistance in high state v bst_ = 6v, lx_ = gnd 3 dl_ on-resistance in low state 1.7 dl_ on-resistance in high state 3 bst_ leakage current v bst_ = 30v, v lx_ = 24v 50 ? lx_ leakage current v bst_ = 30v, v lx_ = 24v 50 ? en and vid_ low level threshold 0.8 v high level threshold 1.6 v pullup resistance internally pulled up to v dd 50 200 k pwrgd pwrgd upper trip level 10 15 % pwrgd lower trip level -15 -10 % output low level 0.4 v output high leakage 1 ? controlled vid change r time = 120k 6.17 7.25 r time = 47k 2.35 2.99 on-the-fly vid change slew rate 25mv per step r time = 470k 23.5 29.9 ? vid_ change frequency range 38 380 khz pwrgd blanking time v vdd = 4.5v to 5.5v 125 350 ? note 1: specifications to -40? are guaranteed by design and not production tested.
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change _______________________________________________________________________________________ 7 efficiency vs. load current at 1.45v output max1937 toc01 load current (a) efficiency (%) 10 60 70 80 90 50 1 100 v in = 8v v in = 14v v in = 12v v out = 1.45v 50 60 70 80 90 1 10 100 efficiency vs. load current at 1.85v output max1937 toc02 load current (a) efficiency (%) v in = 12v v in = 14v v out = 1.85v v in = 8v frequency vs. load current max1937 toc03 load current (a) frequency (khz) 50 40 30 20 10 50 100 150 200 250 300 350 0 060 v in = 12v v out = 1.45v frequency vs. input voltage max1937 toc04 input voltage (v) frequency (khz) 13 12 11 10 9 175 200 225 250 275 300 325 150 814 i load = 46a v out = 1.45v i load = 1a frequency vs. temperature max1937 toc05 temperature ( c) frequency (khz) 80 60 -20 0 20 40 225 230 235 240 245 250 255 260 220 -40 100 v in = 12v v out = 1.45v i load = 10a v cc input current vs. input voltage max1937 toc06 input voltage (v) v cc input current ( a) 13 12 11 10 9 5 10 15 20 25 0 814 v out = 1.45v v dd current vs. v dd voltage max1937 toc07 v dd voltage (v) v dd current (ma) 5.3 5.1 4.9 4.7 1.55 1.60 1.65 1.70 1.75 1.80 1.50 4.5 5.5 typical operating characteristics (v in = 12v, v out = 1.45v, t a = +25?, unless otherwise noted.)
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v in = 12v, v out = 1.45v, t a = +25?, unless otherwise noted.) current sharing max1937 toc10 load current (a) inductor currents (a) 40 30 20 10 0 5 10 15 20 25 30 -5 050 v in = 12v v out = 1.45v t a = +25 c current sharing max1937 toc11 load current (a) inductor currents (a) 40 30 20 10 0 5 10 15 20 25 30 -5 050 v in = 12v v out = 1.45v t a = +80 c v in = 12v v out = 1.45v i out = 0a 0a output inductor currents: 10a/div output ripple voltage: 20mv/div 2 s/div max1937 toc12 inductor current waveforms with 0a load v in = 12v v out = 1.45v i out = 40a output inductor currents: 10a/div output ripple voltage: 20mv/div 2 s/div max1937 toc13 inductor current waveforms with 40a load 0a output voltage vs. load current at 1.45v output max1937 toc09 load current (a) v out 40 30 20 10 1.375 1.400 1.425 1.450 1.350 050 r vpos = 90.9k v in = 12v r vpos = 120k v dd current vs. v dd voltage in shutdown max1937 toc08 v dd voltage (v) v dd current (ma) 5.3 5.1 4.9 4.7 35 40 45 50 55 65 60 70 30 4.5 5.5 vid_ not connected
enable signal output voltage: 0.5v/div pok signal 20ms/div max1937 toc18 shutdown waveform with 40a load inductor current: 10a/div max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change _______________________________________________________________________________________ 9 current-sense threshold vs. v ilim max1937 toc19 v ilim (v) current-sense threshold (mv) 1.3 1.1 0.9 0.7 60 80 100 120 140 160 40 0.5 1.5 v in = 12v v out = 1.45v t a = +25 c t a = +80 c typical operating characteristics (continued) (v in = 12v, v out = 1.45v, t a = +25?, unless otherwise noted.) enable signal output voltage: 0.5v/div pok signal 1ms/div max1937 toc16 soft-start waveforms with 40a load inductor current: 10a/div enable signal output voltage: 0.5v/div pok signal 20ms/div max1937 toc17 shutdown waveform with no load inductor current: 10a/div 40 s/div max1937 toc14 load transient 1a to 40a to 1a transient control signal: c6 = 47pf r2 = 91.1k inductor currents: 10a/div output voltage: 50mv/div enable signal output voltage: 0.5v/div pok signal 1ms/div max1937 toc15 soft-start waveforms with no load inductor current: 10a/div
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 10 ______________________________________________________________________________________ reference voltage vs. temperature max1937 toc22 temperature ( c) reference voltage (v) 80 60 40 20 0 -20 1.992 1.994 1.996 1.998 2.000 1.990 -40 100 v in = 12v v out = 1.45v no load fb voltage vs. temperature max1937 toc23 temperature ( c) fb voltage (v) 60 35 10 -15 0.795 0.800 0.805 0.810 0.790 -40 85 v in = 12v no load v out = 0.8v fb voltage vs. temperature max1937 toc24 temperature ( c) fb voltage (v) 80 60 40 20 0 -20 1.450 1.455 1.460 1.465 1.445 -40 100 v in = 12v no load v out = 1.45v output voltage: 200mv/div pok signal 40 s/div max1937 toc20 vid code change on-the-fly with 40a load 1.2v to 1.45v to 1.2v vid code change control signal output voltage: 200mv/div pok signal 40 s/div max1937 toc21 vid code change on-the-fly with 1a load 1.2v to 1.45v to 1.2v vid control signal typical operating characteristics (continued) (v in = 12v, v out = 1.45v, t a = +25?, unless otherwise noted.)
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change ______________________________________________________________________________________ 11 pin description pin name function 1 vid0 voltage identification input bit 0. see table 1. internal 100k pullup resistor to v dd . 2 vid1 voltage identification input bit 1. see table 1. internal 100k pullup resistor to v dd . 3 time connect to an external resistor (47k to 470k ) for vid change slew-rate control. 4 vid2 voltage identification input bit 2. see table 1. internal 100k pullup resistor to v dd . 5 vid3 voltage identification input bit 3. see table 1. internal 100k pullup resistor to v dd . 6 vid4 voltage identification input bit 4. see table 1. internal 100k pullup resistor to v dd . 7 vpos voltage positioning. connect a resistor between vpos and ref to set the output voltage-positioning droop, or connect directly to ref for no output voltage positioning. connect a 47pf capacitor from vpos to gnd. 8 v dd ic analog power-supply input. connect a 5v supply to v dd . 9 ilim current-limit threshold per phase. connect ilim to v dd to set a default current limit of 120mv, or connect to a voltage-divider from ref to gnd to adjust the current limit. see the setting the current limit section. 10 gnd ground 11 gnds remote ground sense. connect gnds to the output ground at the load. for vrm applications, also connect a 100 resistor from gnds to pgnd locally. 12 ref reference output. connect a 0.1? capacitor from ref to gnd. 13 en enable input. leave unconnected or drive high for normal operation. drive low for shutdown. 14 fb remote feedback sense. connect fb to the output at the load. for vrm applications, also connect a 100 resistor from fb to the output locally. 15 pwrgd power-good output. open-drain output is high impedance when the output is in regulation and pulled low when the output deviates more than 12.5% from the voltage set by the vid code. pwrgd is also low in shutdown or during any fault condition. to use as a logic output, connect a pullup resistor from pwrgd to the logic supply. 16 bst2 high-side mosfet gate-driver bootstrap input. connect 0.22? or higher value bypass capacitor from bst2 to lx2. keep trace length as short as possible. connect a schottky diode between bst2 and vlg. see the selecting a bst capacitor section. 17 dh2 high-side mosfet gate-drive output. connect to the high-side mosfet gate. dh2 is pulled low in shutdown. 18 lx2 inductor connection. connect to the switched side of the inductor. 19 cs2 negative current-sense input. connect to a current-sense resistor in series with the low-side mosfet, or connect to lx2 to use the low-side mosfet? on-resistance for current sensing. 20 dl2 low-side mosfet gate-driver output. connect to the low-side mosfet gate. dl2 is pulled low in shutdown. 21 pgnd power ground. connect to power ground at the point where the current-sense resistors or low-side mosfet sources connect. pgnd is used as the positive current-sense connection.
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 12 ______________________________________________________________________________________ detailed description the max1937/max1938/max1939 is a family of syn- chronous, two-phase step-down controllers capable of delivering load currents up to 60a. the controllers use quick-pwm control architecture in conjunction with active load current voltage positioning. quick-pwm control provides instantaneous load-step response, while programmable voltage positioning allows the con- verter to utilize full transient regulation limits, reducing the output capacitance requirement. furthermore, the two phases operate 180 out-of-phase with an effective 500khz switching frequency, thus reducing input and output current ripple, as well as reducing input filter capacitor requirements. the max1937/max1938/max1939 are compliant with the amd hammer, intel vrm 9.0/vrm 9.1, and amd athlon mobile vid code specifications (see table 1 for vid codes). the internal dac provides ultra-high accu- racy of ?.75%. a controlled vid voltage transition is implemented to minimize both undervoltage and over- voltage overshoot during vid input change. remote sensing is available for high output-voltage accuracy. the mosfet switches are driven by with a 6v gate-drive circuit to minimize switching and crossover conduction losses to achieve efficiency as high as 90%. the max1937/max1938/ max1939 fea- ture cycle-by-cycle current limit to ensure current limit is not exceeded. crowbar protection is available to pro- tect against output overvoltage. on-time one-shot the heart of the quick-pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, one-shot circuitry varies the on-time in response to the input and output voltages. the high-side switch on-time is inversely proportional to the voltage applied to v cc and directly proportional to the output voltage. this algorithm results in a nearly constant switching fre- quency, despite the lack of a fixed-frequency clock generator. the benefits of a constant switching fre- quency are twofold: the frequency selected avoids noise-sensitive regions, and the inductor ripple current operating point remains relatively constant, resulting in easy design methodology and predictable output volt- age ripple: where the constant k is 4? and v drop is the voltage drop across the low-side mosfet? on-resistance plus the drop across the current-sense resistor (v drop 75mv), if used. the on-time one-shot has good accuracy at the operat- ing point specified in the electrical characteristics . on- times at operating points far removed from the conditions specified in the electrical characteristics can vary over a wide range. for example, the regulators run slower with input voltages greater than 12v because of the very short on-times required. t kv v v on out drop vcc = + () pin description (continued) pin name function 22 vlg dl_ driver power-supply input. connect to a 4.5v to 6.5v supply for powering the low-side mosfet gate drive, and the bootstrap circuit for driving the high-side mosfets. ensure that v vlg is greater than or equal to v vdd . 23 dl1 low-side mosfet gate-driver output. connect to the low-side mosfet gate. dl1 is pulled low in shutdown. 24 cs1 negative current-sense input. connect to a current-sense resistor in series with the low-side mosfet or connect to lx1 to use the low-side mosfet? on-resistance for current sensing. 25 lx1 inductor connection. connect to the switched side of the inductor. 26 dh1 high-side mosfet gate-drive output. connect to the high-side mosfet gate. dh1 is pulled low in shutdown. 27 bst1 high-side mosfet gate-driver bootstrap input. connect 0.22? or higher value bypass capacitor from bst1 to lx1. keep trace length as short as possible. connect a schottky diode between bst1 and vlg. see the selecting a bst capacitor section. 28 v cc input voltage sense. connect to the input supply at the high-side mosfet drain. the voltage sensed at v cc is used to set the on-time.
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change ______________________________________________________________________________________ 13 while the on-time is set by the input and output voltage, other factors contribute to the switching frequency. the on-time guaranteed in the electrical characteristics is influenced by switching delays in the external high-side mosfet. resistive losses in the inductor, both mosfets, output capacitor esr, and pc board copper losses in the output and ground, tend to raise the switching fre- quency at higher output currents. switch dead-time can also increase the effective on-time, reducing the switching frequency. this effect occurs when the inductor current reverses at light or negative load cur- rents. with reversed inductor current, the inductor? v out (v) vid4 vid3 vid2 vid1 vid0 max1937 max1938 max1939 00000 1.550 1.850 2.000 00001 1.525 1.825 1.950 00010 1.500 1.800 1.900 00011 1.475 1.775 1.850 00100 1.450 1.750 1.800 00101 1.425 1.725 1.750 00110 1.400 1.700 1.700 00111 1.375 1.675 1.650 01000 1.350 1.650 1.600 01001 1.325 1.625 1.550 01010 1.300 1.600 1.500 01011 1.275 1.575 1.450 01100 1.250 1.550 1.400 01101 1.225 1.525 1.350 01110 1.200 1.500 1.300 01111 1.175 1.475 shutdown 10000 1.150 1.450 1.275 10001 1.125 1.425 1.250 10010 1.100 1.400 1.225 10011 1.075 1.375 1.200 10100 1.050 1.350 1.175 10101 1.025 1.325 1.150 10110 1.000 1.300 1.125 10111 0.975 1.275 1.100 11000 0.950 1.250 1.075 11001 0.925 1.225 1.050 11010 0.900 1.200 1.025 11011 0.875 1.175 1.000 11100 0.850 1.150 0.975 11101 0.825 1.125 0.950 11110 0.800 1.100 0.925 11111 shutdown shutdown shutdown table 1. vid programmed output voltage note: in the above table, a zero indicates the vid_ pin is connected to gnd or driven low, indicates the vid_ pin is driven high or not connected.
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 14 ______________________________________________________________________________________ emf causes lx to go high earlier than normal, extend- ing the on-time by a period equal to the dh rising dead-time. when the controller operates in continuous mode, the dead-time is no longer a factor, and the actual switch- ing frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including the synchro- nous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path, including the high-side mosfet, inductor, and pc board resistances. synchronized 2-phase operation the two phases of the max1937/max1938/max1939 operate 180 out-of-phase to reduce input filtering requirements, reduce electromagnetic interference (emi), and improve efficiency. this effectively lowers cost and saves board space, making the max1937/ max1938/max1939 ideal for cost-sensitive applica- tions. with dual synchronized out-of-phase operation, the max1937/max1938/max1939s?high-side mosfets turn on 180 out-of-phase. the instantaneous input current peaks of both regulators do not overlap, resulting in reduced input voltage ripple and rms ripple current. this reduces the input capacitance requirement, allowing fewer or less expensive capacitors, and reduces shield- ing requirements for emi. the 180 out-of-phase wave- forms are shown in the typical operating characteristics. each phase operates with a 250khz switching frequen- cy. since the two regulators operate 180 out-of-phase, an effective switching of 500khz is seen at the input and output. in addition to being at a higher frequency (compared to a single-phase regulator), both the input and output ripple have lower amplitude. phase overlap to minimize the crosstalk noise in the two phases, the maximum duty cycle of the max1937/max1938/ max1939 is less than 50%. to provide a fast transient response, these devices have a phase-overlap mode that allows the two phases to operate in phase when a heavy-load transient is detected. in-phase operation continues until the output voltage returns to the nominal output voltage regulation value. once regulation is achieved, the controller returns to 180 out-of-phase operation. a minimum current-adap- tive phase-selection algorithm is used to determine which phase is used to start the first out-of-phase cycle. once the output voltage returns to the nominal output voltage regulation value, the subsequent cycle starts with the phase that has the lowest inductor current. for example, if the current-sense inputs indicate that phase 2 has lower inductor current than phase 1, the controller turns on phase 2? high-side mosfet first when returning to normal operation. differential voltage sensing and error comparator the max1937/max1938/max1939 use differential sensing of the output voltage to achieve the highest possible accuracy of the output voltage. this allows the error comparator to sense the actual voltage at the load, so that the controller can compensate for losses in the power output and ground lines. fb and gnds are used for the differential output voltage sensing. the controller triggers the next cycle (turn on the high-side mosfet) when the error comparator is low (v fb - v gnds is less than the vid regulation voltage), v cs is below the current-limit threshold, and the mini- mum off-time one-shot has timed out. traces from fb and gnds should be routed close to each other and as far away as possible from sources of noise (such as the inductors and high di/dt traces). if noise on these connections cannot be prevented, then use rc filters. to filter fb, connect a 100 series resistor from the positive sense trace to fb, and connect a 1000pf capacitor from fb to gnd right at the fb pin. for gnds, connect a 100 series resistor from the negative sense trace to gnds, and connect a 1000pf capacitor from gnds to gnd at the gnds pin. for vrm applications, connect a 10k resistor from fb to the output locally (on the vrm board), and connect a 10k resistor from gnds to pgnd locally (on the vrm board). fb and gnds also connect to the output at the load (off the vrm board, at the microprocessor). this provides the benefits of differential output voltage sens- ing mentioned above and the safety of regulating the output voltage on the board in case the external sense connections get disconnected. external linear regulator a 6v linear regulator (u2) is used to step down the main supply. the output of this linear regulator is con- nected to vlg to provide power for the low-side gate drive and bootstrap circuit. using 6v for this supply improves efficiency by providing a stronger gate drive than a 5v supply. to reduce switching noise on vlg, f vv tv v v sw out drop on vcc drop drop = + + () ? 1 12
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change ______________________________________________________________________________________ 15 connect a capacitor (c vlg ) from vlg to pgnd. place this capacitor as close as possible to the vlg pin. the max1937/max1938/max1939 also require an exter- nal 5v supply connected to v dd . a diode with a forward voltage drop of about 1v (d1) is used to stepdown the 6v supply to power the ic, as shown in figure 1. the diode connects between the linear regulator output and the rc filter used to filter the voltage at v dd (r1, c vdd , and c3). in the pc board layout, place c vdd as close as possible to the v dd pin. high-side gate-drive supply (bst_) the drive voltage for the high-side mosfets is gener- ated using a bootstrap circuit. the capacitor, c bst_ , should be sized properly to minimize the ripple voltage for switching. the ripple voltage should be less than 200mv. for more information on selecting capacitors for the bst circuit, see the selecting a bst capacitor section. to minimize the forward voltage drop across the bootstrap diodes (d2), use schottky diodes. the recommended value for the boost capacitors (c bst_ ) is 0.22?. r2 100k v cc v dd vid4 en gnds time vpos gnd ref bf pwrgd lx2 dh2 ilim gnds 6 10 f ceramic capacitors taiyo yuden tmk432bj106mm and 2 100 f os-con sanyo 16sp100m ir: 2 irlr7811w 6 390 f sp-cap panasonic eefue0d391xr and 4 1 f ceramic capacitors taiyo yuden lmk212bj105mg c vlg 1 f c3 2.2 f c vdd 0.01 f vid4 en n2 n3 l2 0.66 h sumida cdep134-6 ir: 2 1rlr7811w fairchild 2 isl9n303as3st d2 central cmpsh-3a fairchild 2 isl9n303as3st r5 10k r4 68k c ref 0.47 f c vpos 47pf r3 200k r1 10 pwrgd c out v out fb vdd l1 0.66 h sumida cdep134-6 c1 2.2 f r vpos 51.1k r time 120k u1 max1937 r6 10k 28 8 6 13 vid2 vid3 vid2 vid1 vid0 d1 gnd u2 ka78m06 central cmhd4448 2 3 2 out in 1 1 vid3 4 5 vid0 vid1 1 2 3 7 12 9 10 11 18 17 14 1 2 2 2 c bst2 0.22 f c bst1 0.22 f 3 dl2 n4 20 cs2 19 pgnd 21 vlg cs1 22 24 dl1 23 bst1 27 lx1 25 dh1 26 bst2 16 1 1 1 1 3 3 n3 2 3 n1 c in input: 8v to 14v output 0.8v to 1.55v 46a 3 2 13 v in vdd 1m r cs2 1m r cs1 c2 2.2 f v in figure 1. max1937 application circuit
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 16 ______________________________________________________________________________________ mosfet drivers the dh_ and dl_ drivers are optimized for driving large high-side (n1 and n2) and larger low-side mosfets (n3 and n4). this is consistent with the low duty-cycle operation of the controller. the dl_ low-side drive wave- form is always the complement of the dh_ high-side drive waveform, with a fixed dead-time between one mosfet turning off and the other turning on to prevent cross-conduction or shoot-through current. the internal transistor that drives dl_ low is robust with a 0.5 (typ) on-resistance. this helps prevent dl_ from being pulled up during the fast rise time of the lx_ node due to capacitive coupling from the drain to the gate of the low-side synchronous-rectifier mosfet. however, some combinations of high-side and low-side mosfets may cause excessive gate-drain coupling, leading to poor efficiency, emi, and shoot-through cur- rents. this is often remedied by adding a resistor (typi- cally less than 5 ) in series with bst_, which increases the turn-on time of the high-side mosfet without degrading the turn-off time. current-limit circuit the max1937/max1938/max1939 use either the on- resistance of the low-side mosfets or a current-sense resistor to monitor the inductor current. using the low- side mos fets?on-resistance as the current-sense ele- ment provides a lossless and inexpensive solution ideal for high-efficiency or cost-sensitive applications. the dis- advantage to this method is that the on-resistance of mosfets vary from part to part, and overtemperature, which means it cannot be counted on for high accuracy. if high accuracy is needed, use current-sense resistors, which provide an accurate current limit under all condi- tions but reduce efficiency slightly because of the power lost in the resistors. the current-limit circuit employs a ?alley?current- sensing algorithm to monitor the inductor current. if the current-sense signal does not drop below the current- limit threshold, the controller does not initiate a new cycle. this limits the maximum value of i valley to the current set by the current-limit threshold (figure 2). the current-limit threshold is adjustable over a wide range, allowing for a range of current-sense resistor values. the voltage on ilim sets the current-limit threshold between pgnd and cs_ to 0.1 ? v ilim . the 10mv to 200mv adjustment range corresponds to ilim voltages from 100mv to 2v. the ilim voltage is set by a resistor-divider between ref and gnd. see the setting the current limit section for details. current balancing the dc current balancing between phases depends on the accuracy of the current-sense elements and the off- set of the current-balance amplifier. the maximum offset of the current-balance amplifier (v cboffset ) is ?mv. the current-balance accuracy can be calculated from: current-balance accuracy = v cboffset / (i l ? r cs ) where i l is the peak inductor current and r cs is the value of the current-sense resistor. the current-balance accuracy is most important at full load. with a load current of 50a (i l = 25a) and 2m current-sense resistors, the worst-case current-balance accuracy is: current-balance accuracy = 0.003 / (25 ? 0.002) = 6% if the on-resistance of the low-side mosfets is used for current sensing, the part-to-part variation of the mosfet on-resistance is a significant factor in the cur- rent balance. the matching between mosfets should be on the order of 15%, worst case. thus, even if the current-balance amplifier has no offset, the dc-current balance could be as bad as 15%. in practice, a little help is received from the thermal ballasting of the mosfets. that is to say, the positive temperature coef- ficient of the on-resistance of mosfets reduces the mismatch current between the two phases. voltage positioning (vpos) during a load transient, the output voltage instantly changes by the esr of the output capacitors times the change in load current ( v out = -esr cout ? i load ). conventional dc-dc converters respond by regulating the output voltage back to its nominal state after the load transient occurs (figure 3). however, the cpu requires that the output voltage remain within a specific voltage band. dynamically positioning the output volt- age allows the use of fewer output capacitors and reduces power consumption under heavy load. for a conventional (nonvoltage-positioned) circuit, the total output voltage deviation from light load to full load and back to light load is: v p-p1 = 2 ? (esr cout ? i load ) + v sag + v soar where v sag and v soar are defined in the output capacitor selection section. setting the converter to regulate at a lower voltage when under load allows a larger voltage step when the output current suddenly decreases. the total voltage change for a voltage-posi- tioned circuit is: v p-p2 = (esr cout ? i load ) + v sag +v soar
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change ______________________________________________________________________________________ 17 the maximum allowable voltage change during a tran- sient is fixed by the supply range of the cpu (v p-p1 = v p-p2 ). this means that the voltage-positioned circuit tolerates twice the esr in the output capacitors. because the esr specification is achieved by parallel- ing several capacitors, fewer capacitors are needed for the voltage-positioned circuit. figure 4 shows transient response regions. an additional benefit of voltage positioning is reduced power consumption at high-load currents. because the output voltage is lower under heavy load, the cpu draws less current. the result is lower power dissipa- tion in the cpu. voltage reference (ref) a 2v reference is provided on the max1937/max1938/ max1939 through the ref pin. ref is capable of sourcing or sinking up to 50?. in addition to providing a reference for the ic, ref is used for setting the cur- rent limit and voltage positioning. connect a 0.47? capacitor from ref to gnd. this capacitor should be placed as close as possible to the ref pin. a uvlo is provided for the reference voltage. the ref- erence voltage must rise above 1.600v to activate the controller. the controller is disabled if the reference voltage falls below 1.584v. enable input (en) and soft-start when en is low, dl_ and dh_ are held low (turning off the mosfets), leaving lx_ high impedance. in addi- tion, the reference is turned off and pwrgd is pulled low. in shutdown, total current consumption is about 50? (typ). in the case of shutdown by vid code, only dl_ and dh_ are held low. the rest of the controller is enabled. when en is driven high, the startup sequence begins. once the reference voltage rises above its 1.6v uvlo threshold, the controller begins switching and starts to ramp up the output voltage. the output voltage is ramped up in 25mv steps every 50? until the output reaches the nominal output voltage. fault conditions the max1937/max1938/max1939 contain internal cir- cuitry to protect themselves and surrounding circuitry from damage from output overvoltage and output undervoltage conditions. when either of these condi- tions occurs, dh_ is pulled low, dl_ is driven high, and pwrgd is pulled low. these pins remain in this state until either power is cycled on v dd or en is toggled high-low-high. setting the output voltage (vid_) an internal dac is used to set the output regulation voltage. a 5-bit code on inputs vid0?id4 is used to specify the output voltage. some codes disable the output. there is an internal 100k pullup resistor to vdd on each of the vid_ inputs. connecting vid_ to gnd sets the bit to logic low (0); connecting vid_ to vdd or leaving it unconnected sets the bit to logic high (1). use external pullup resistors to speed the low-to- high logic transition, or for lower logic voltages. see table 1 for a list of codes and corresponding output regulation voltages for each of the parts. the vid_ codes for the max1937 comply with amd hammer code. the vid_ codes on the max1938 are inductor current time i peak i load i valley figure 2. inductor current waveform b 1.4v 1.4v a a. conventional converter (50mv/div) b. voltage-positioned output (50mv/div) voltage positioning the output figure 3. voltage-positioning and nonvoltage-positioning waveforms
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 18 ______________________________________________________________________________________ set for intel vrm 9.0/9.1 and amd athlon. the max1939 is set for amd athlon mobile. vid_ change slew rate (time) the max1937/max1938/max1939 allow the vid_ code to be changed while the converter is operating (on-the- fly). the slew rate at which the output voltage is chang- ing is controlled through time. the slew rate is adjusted externally by connecting a 47k to 470k resistor (r time ) from time to gnd. to set the slew rate, select the r time resistor using the following equation: where sr is the slew rate of the output voltage in v/?. the output voltage is stepped up or down in 25mv steps until it reaches the voltage set by the new vid code. power-good output (pwrgd) pwrgd is an open-drain output that is pulled low when the output voltage deviates more than 12.5% from its regulation voltage (set by vid_ inputs). pwrgd is pulled low in shutdown, input uvlo, and during start- up. any fault condition forces pwrgd low until the fault is cleared, and the ic is reset by cycling power at v dd or momentarily toggling en. for logic-level output volt- ages, connect an external pullup resistor between pwrgd and the logic power supply. a 100k resistor works well in most applications. design procedure output inductor selection for most applications, an inductor value of 0.5? to 1? is recommended. the inductance is set by the desired amount of inductor current ripple (lir). a larger inductance value minimizes output ripple current and increases efficiency, but slows transient response. for the best compromise of size, cost, and efficiency, a lir of 30% to 40% is recommended (lir = 0.3 to 0.4). the inductor value is found from: where f sw is the actual switching frequency of a phase. the selected inductor should have the lowest possible equivalent dc resistance and a saturation current greater than the peak inductor current (i peak ). i peak is found from: output capacitor selection the output capacitor must have low enough esr to meet output ripple and load-transient requirements. also, the capacitance value must be high enough to absorb the inductor energy going from a full-load to a no-load condition without tripping the ovp circuit. in cpu core power supplies and other applications where the output is subject to large load transients, the output capacitor? size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: r esr = v step(max) / i load(max) the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of os- cons, sp capacitors, poscaps, and other electrolytic capacitors). generally, ceramic capacitors are not rec- ommended for bulk output capacitance but make excellent high-frequency decoupling capacitors. once enough capacitance is added to meet the over- shoot requirement, undershoot at the rising load edge ii lir peak load max =+ ? ? ? ? ? ? () 1 2 l vvv v f i lir out in out in sw load max = ? () () r sr time = 521 () v out esr voltage step (i step x r esr ) capacitive soar (dv/dt = i out /c out ) recovery capacitive sag (dv/dt = i out /c out ) i load figure 4. transient response regions
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change ______________________________________________________________________________________ 19 (v sag ) is no longer a problem. the amount of overshoot from stored inductor energy can be calculated as: where i peak is the peak inductor current. the undershoot at the rising load edge of a load tran- sient is calculated from: where i load is the change in load current, and k is 4?. to ensure stability, make sure that the zero frequency created by the output capacitance, and the esr of the output capacitor do not exceed 50khz. the zero fre- quency is found from: currently, aluminum electrolytic, sanyo poscap, and panasonic sp capacitors have esr zero frequencies well below 50khz. when using ceramic capacitors, it might be necessary to use a series resistance to ensure that the esr zero is below 50khz. input capacitor selection the input capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit? switching. the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents as defined by the following equation: i rms has a maximum value when the input voltage equals twice the output voltage (v in = 2v out ), so i rms(max) = i load / 2. for most applications, nontanta- lum capacitors (ceramic, aluminum electrolytic, poly- mer, or os-con) are preferred at the input because of their robustness with high inrush currents typical of sys- tems that may be powered from very low impedance sources. multiple smaller value capacitors can be used in paral- lel to satisfy the esr and capacitance requirements. selecting a bst capacitor the bst capacitors must be large enough to handle the gate-charging requirements of the high-side mosfets. for most applications, 0.22? ceramic capacitors are recommended. bst capacitors are needed to keep the voltage on the bst_ pins from dropping too much when the high-side mosfet gates are charged. a capacitor value that prevents v bst _ from dropping more than 100mv to 200mv is adequate. the capacitance needed for the bst_ capacitor is calculated from: where q gh is the total gate charge of the high-side mosfet and v bst_ is the amount that the voltage on the bst_ pin drops when the gate is charged. if using multiple mosfets in parallel, use the sum of all the gate charges for q gh . setting the current limit current limit sets the maximum value of the inductor ?alley?current. i valley is calculated from the following equation: the current-limit threshold (i limit ) must be set higher than the valley current: the current-limit threshold is set by the voltage at ilim and the value of the current-sense resistors: where v ilim is the voltage on the ilim pin (0.1v to 2v) and r cs is the value of the current-sense resistor. if the on-resistance of the low-side mosfet is used for cur- rent sensing, then the maximum value of the on-resis- tance (overtemperature and part-to-part variation) must be used for r cs . i v r limit ilim cs = 10 ii limit valley > i i lir valley load max =? ? ? ? ? ? ? () 2 1 2 c q v bst gh bst _ _ = i i vvv v rms load out in out in = ? () 2 f esr c zesr cout out = 1 2 v li vk v t cv vv k v t sag load out in off min out out in out in off min = + ? ? ? ? ? ? ? ? ? ? ? 2 2 () () () v il cv soar peak out out = 2 2
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 20 ______________________________________________________________________________________ v ilim is set from 0.5v to 2v by connecting ilim to a resistor-divider from ref to gnd. select resistors r3 and r4 such that the current through the divider is at least 5?: a typical value for r3 is 200k ; then solve for r4 using: setting the voltage positioning voltage positioning dynamically changes the output- voltage set point in response to the load current. when the output is loaded, the signals fed back from the cur- rent-sense inputs adjust the output voltage set point, thereby decreasing power dissipation. the load-tran- sient response of this control loop is extremely fast yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor power-supply guidelines. to under- stand the benefits of dynamically adjusting the output voltage, see the voltage positioning (vpos) section. the amount of output voltage change is adjusted by an external gain resistor (r vpos ). connect r vpos between ref and vpos. the output voltage changes in response to the load current as follows: where v vid is the programmed output voltage set by the vid code (table 1), and the voltage-positioning transconductance (g m(vpos) ) is typically 20?. r cs is the value of the current-sense resistor connected from cs_ to pgnd. if the on-resistance of the low-side mosfets is used instead of current-sense resistors for current sensing, then use the maximum on-resistance of the low-side mosfets for r cs in the equation above. mosfet power dissipation power dissipation in the high-side mosfet is worst at high duty cycles (maximum output voltage, minimum input voltage). two major factors contribute to the high- side power dissipation, conduction losses, and switch- ing losses. conduction losses are because of current flowing through a resistance, and can be calculated from: where r ds(on) is the on-resistance of the high-side mosfet and v in is the input voltage. to minimize con- duction losses, select a mosfet with a low r ds(on) . switching losses are also a major contributor to power dissipation in the high-side mosfet. switching losses are difficult to precisely calculate and should be mea- sured in the circuit. to estimate the switching losses, use the following equation: where i peak and i valley are the maximum peak and valley inductor currents, t fall and t rise are the fall and rise times of the high-side mosfet, and f sw is the switching frequency (about 250khz). the total power dissipated in the high-side mosfet is then found from: p d(hs) = p d(hs)cond + p d(hs)sw the power dissipation in the low-side mosfet is high- est at low duty cycles (high input voltage, low output voltage), and is mainly because of conduction losses: switching losses in the low-side mosfet are small because of its voltage being clamped by the body diode. switching losses can be estimated from: where i loadmax/2 is the maximum average inductor current, t dt is the time/cycle that the low-side mosfet conducts through its body diode, and v df is the for- ward voltage drop across the body diode. the total power dissipation in the low-side mosfet is: p d(ls) = p d(ls)cond + p d(ls)sw ic power dissipation during normal operation, power dissipation in the con- troller is mostly from the gate drivers. this can be cal- culated from the following equation: p gate = 2 ? v vlg ? f sw ? ( q gh + q gl ) p i tvf dlssw loadmax dt df sw () ? 2 p v v i r d ls cond out in loadmax ds on () ( ) =? ? ? ? ? ? ? 1 4 2 pitit vf d hs sw peak fall valley rise in sw () () ?+ 2 p vi r v d hs cond out loadmax ds on in () () = 2 4 vvg r ir out vid m vpos vpos out cs =? ? ? ? ? ? ? () 2 rr v v ilim ilim 43 2 = ? rr k 3 4 400 +
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change ______________________________________________________________________________________ 21 where f sw is approximately 250khz, q gh is the gate charge of the high-side mosfet, and q gl is the gate charge of the low-side mosfet. the values used for the gate charge are at the gate drive voltage (v vlg ). the ??in the above equation is due to the two phases of the converter. if multiple mosfets are used in paral- lel, add the gate charges of each mosfet to find the total gate charge used in the above equation. make sure that the maximum power dissipation of the ic is not exceeded (see the absolute maximum ratings ). applications information pc board layout guidelines a properly designed pc board layout is important in any switching dc-dc converter circuit. if possible, mount the mosfets, inductor, input/output capacitors, and current-sense resistor on the top side of the pc board. connect the ground for these devices close together on a power ground plane. make all other ground connec- tions to a separate analog ground plane. connect the analog ground plane to power ground at a single point. to help dissipate heat, place high-power components (mosfets, inductor, and current-sense resistor) on a large pc board area, or use a heat sink. keep high cur- rent traces short and wide to reduce the resistance in these traces. also make the gate-drive connections (dh_ and dl_) short and wide, measuring 10 to 20 squares (50mils to 100mils wide if the mosfet is 1in from the controller ic). use kelvin sense connections for the current-sense resistors. place the ref capacitor, the v dd capacitor, and the bst_ diode and capacitor as close as possible to the ic. if the ic is far from the input capacitors, bypass v cc to gnd with an additional 0.1? or greater ceramic capaci- tor close to the v cc pin. for an example pc board layout, refer to the max1937 or max1938 evaluation kit. chip information transistor count: 6243 process: bicmos
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change 22 ______________________________________________________________________________________ control logic on-time compute current balance current limit uvlo/ ovlo vcc cs1 cs2 cs1 cs2 fb vlg bst1 dh1 lx1 vlg dl1 pgnd bst2 dh2 lx2 dl2 dl2 dl2 on-time one-shot bias enable/ shutdown min off time one-shot vdd pwrgd vpos ref fb 2v gnds error amp vid dac gnd vid0?id4 time ilim ref - 12.5% ref + 12.5% en g m functional diagram
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change ______________________________________________________________________________________ 23 r2 100k v cc v dd vid4 en gnds time vpos gnd ref bf pwrgd lx2 dh2 ilim gnds 10 10 f ceramic capacitors taiyo yuden tmk432bj106mm and 4 330 f sanyo 25mv330wx 6 560 f/4v os-can capacitors sanyo sp560m and 2 1 f ceramic capacitors taiyo yuden: lmk212bj105mg cvlg 1 f c3 2.2 f c vdd 0.01 f vid4 en n2 n3 l2 0.5 h bi technologies hm73-40r50 ir: 2 1rlr7811w fairchild 2 1sl9n303as3st d2 central cmpsh-3a fairchild 2 1sl9n303as3st r5 10k r4 82.5k c ref 0.47 f c vpos 47pf r3 200k r1 10 pwrgd v out fb vdd l1 0.5 h bi technologies hm73-40r50 c1 2.2 f r vpos 51.1k r time 120k u1 max1938 r6 10k 28 8 6 13 vid2 vid3 vid2 vid1 vid0 d1 gnd u2 ka78m06 central cmhd4448 2 3 2 out in 1 1 vid3 4 5 vid0 vid1 1 2 3 7 12 9 10 11 18 17 14 1 2 2 2 c bst2 0.22 f cbst1 0.22 f 3 dl2 n4 20 cs2 19 pgnd 21 vlg cs1 22 24 dl1 23 bst1 27 lx1 25 dh1 26 bst2 16 1 1 1 1 3 3 n3 2 3 n1 c in input: 8v to 14v output 0.8v to 1.55v 60a 3 2 13 v in vdd 1m r cs2 1m r cs1 c2 2.2 f v in ir: 3x1rlr7811w ir: 3 1rlr7811w max1938 typical application circuit
max1937/max1938/max1939 two-phase desktop cpu core supply controllers with controlled vid change maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qsop.eps f 1 1 21-0055 package outline, qsop .150", .025" lead pitch

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